Your memory speeds can be tricky. This is because, like the CPU`s FSB, it has rated and actual speeds.
For example, DDR2-800, is DDR2 memory rated at 800Mhz. However, that is its rated (Dual Data Rate) speed. The memory is actually only running at 400Mhz, but since data is being read on both peaks of each cycle, its rated speed is doubled. For example, a CPU with a FSB of 266.66Mhz will be in a 1:1 ratio with memory at 266.66Mhz (DDR2-533)
People are confused (misinformed) as to what ratio is optimal for system performance. When looking at the bandwidth in terms of MB/s, your memory needs to be operating 2 times as fast as the CPU`s FSB in order to match the CPU`s L2 bandwidth. If you want to calculate your CPUâs or memoryâs bandwidth you simply multiply the actual frequency by .016. This will give you the maximum theoretical bandwidth in GB/s.
For Example:
DDR2-800 has an actual speed of 400Mhz. 400Mhz x .016 = 6.4GB/s maximum bandwidth.
So, for optimal settings a CPU with a FSB of 266.66Mhz would want memory running at 533Mhz (DDR2-1066). However, this is highly unlikely that you will have memory that can run in a 2:1 ratio with your FSB. A 1:1 ratio is more often the target ratio as it is easier to reach with most memory.
If you want to calculate FSB bandwidth of a Core 2 Duo you multiply bus frequncy (266.66) times the transfers per clock (4) and the FSB width (64bit or 8 byte).
Therefore, a system with a 266.66Mhz FSB (stock Core 2 Duo) has a FSB bandwidth of:
266.66 x 4 x 8 = 8533.33MB/s
Your memory has a 64bit (8 byte) width and a capability of 2 transfers per clock (DDR).
Therefore, to flood the FSB bandwidth you get:
8533.33MB/s = X Mhz * 2 * 8 8533.33MB/s = X Mhz * 16 533.33Mhz = X
Therefore a memory bus speed of 533.33Mhz or DDR2-1066 will flood the FSB bandwidth.
Memory also has a series of latencies. Latencies are measured in terms of clock cycle delays. In order to understand how the latencies work, you must also understand how the memory reads and writes data.
DDR2 memory is a type of SDRAM. SDRAM stands for Synchronous Dynamic Random Access Memory. The memory is organized like a matrix or chart, with data arranged in rows and columns. The data is stored in blocks whose location are found by the coordinates of the specific rows and columns. Latencies come from the memory looking for the data in these series of rows and columns. The four most common latencies are: ⢠Column Address Strobe Latency (tCAS / CAS / tCL). This is the number of clock cycles needed to access a specific column of data. ⢠Row Address Strobe (tRCD, RAS). This is the number of clock cycles that it takes for the memory to actually start reading or writing from the time the coordinates of the data are defined. ⢠Row Precharge time (tRP) and is the number of clock cycles needed to end access to one row of memory and open access to the next row of memory. ⢠Active to Precharge Delay (tRAS) and is the number of clock cycles needed to access a specific row of data in the memory between the data request and the pre-charge command. So what you have are 4 series of latencies. If you didnât get much of the above paragraph, get this. The lower the latencies the better for system performance. However, lower latencies mean less stability at any given voltage. Common value of latencies are 3-3-3-X, 4-4-4-X, 5-5-5-X. The reason I put X in the last spot is because the latencies in this sport vary greatly, but are most commonly between 4 and 18 clock cycles.
Simply comparing memory latencies with considering the speed at which the memory is running those latencies is silly. This is because the overall latencies in nano-seconds is derived from dividing your total latencies in cycles by how many cycles your RAM can complete in one second. This gives you latencies per operation in seconds.
For example:
DDR2-800 does 800,000,000 cycles per second. Latencies of 4-4-4-12 add up to 24 cycles per operation of latency. Divide 24 cycles of latencies by 800,000,000 cycles and you get 30 nano-seconds worth of latencies per operation. However, DDR2-1000 with latencies of 5-5-5-15 also net you the same 30 nano-seconds of latencies per operation (30 / 1,000,000,000).
However, even though both settings have the same latencies. DDR2-1000 @ 5-5-5-15 is better than DDR2-800 @ 4-4-4-12, this is because DDR2-1000 has more data throughput when compared to DDR2-800.
Now, it is also a common myth that a system will be faster when it is `synced` (i.e. in a 1:1 ratio as apposed to a 5:4 ratio) with the processor. This is simply not true (or there is no substantial evidence to prove that it is true). Most people who will claim this and provide benchmarks are often missing a variable that would explain the difference in performance.
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